In a stacked semiconductor device including a plural number of memory chips stacked together, such as a memory module, an SDRAM (Synchronous Dynamic Random Access Memory), latching a variety of control signals by a rising edge of a fundamental input clock signal (CK signal) to input/output data in synchronization with the CK signal, is in widespread use. The SDRAM uses only the rising edge of the CK signal, whereas a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) uses both the rising and falling edges of a data strobe signal (DQS signal) to input/output data to implement a double volume data transmission with the same CK signal. This DQS signal is a control signal for inputting/outputting data per cycle.
In contrast to the DDR SDRAM, pre-fetching two bits, the DDR2 SDRAM (Double Data Rate 2 Synchronous Dynamic Random Access Memory), pre-fetching redoubled bits, that is, four bits, has been developed. The DDR SDRAM uses a data strobe signal (DQS signal) to minimize the timing skew (timing distortion) generated between the memory and a memory controller upon data input/output. The DDR2 SDRAM uses a differential data strobe signal (DQS signal) and an inverted differential data strobe signal (/DQS signal). The DQS signal and the /DQS signal may be changed by EMRS (Extended Mode Register Set) and hence may be used as the same single-ended DQS signal as that used in the DDR SDRAM. In the DDR SDRAM and in the DDR2 SDRAM, the data signals (DQ signals) and the DQS signal are transmitted from a memory controller to a memory during the data write and from the memory to the memory controller during data readout. That is, the DQ signal and the DQS signal are bi-directionally transmitted between the memory and the memory controller. In general, one DQS signal is allocated per 4 bits of data with an SDRAM having a ×4 bit constitution and per 8 bits of data with an SDRAM having a ×8 bit constitution.
In the routine DDR SDRAM and DDR2 SDRAM, the JEDEC standard specification holds as a specification for data readout between the CK and the DQS signals. That is, in the case of a data transmitting rate of 400 Mbps, a skew between the CK and DQS signals (TDQSCK) up to ±500 [ps] is allowed, as indicated by an output timing for the DDR2 SDRAM2 of FIG. 16. In other words, the allowed interval between the shortest period of time and the longest period of time from outputting of the CK signal until outputting the DQS signal is 1000 [ps]. It is noted that TDQSCK(min) indicates the earliest timing at which the DQS signal is output from the DDR2 SDRAM to the memory controller, with the edge of the CK signal as reference, and that TDQSCK(max) indicates the latest timing at which the DQS signal is output from the DDR2 SDRAM to the memory controller, with the edge of the CK signal as reference.
Meanwhile, as a technique which enables an increased storage capacity per unit volume and high density packaging, there has been disclosed in e.g., Patent Document 1 a memory module in which two memory chips are assembled together back-to-back in a stacked configuration (stacked semiconductor device) (see Patent Document 1).
[Patent Document 1] JP Patent Kokai Publication No. JP-P2004-158892A (FIG. 5)
[Patent Document 2] JP Patent Kokai Publication No. JP-P2002-169721A
[Patent Document 3] JP Patent Kokai Publication No. JP-P2005-156328A
[Patent Document 4] JP Patent Kokai Publication No. JP-A-11-202970